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| 1 ltc1709-8/ltc1709-9 features descriptio u applicatio s u typical applicatio n u , ltc and lt are registered trademarks of linear technology corporation. opti-loop is a trademark of linear technology corporation. the ltc ? 1709-8/ltc1709-9 are 2-phase, vid program- mable, synchronous step-down switching regulator con- trollers that drive two all n-channel external power mosfet stages in a fixed frequency architecture. the 2-phase controller drives its two output stages out of phase at frequencies from 150khz to 300khz to minimize the rms ripple currents in both input and output capacitors. the 2- phase technique effectively multiplies the fundamental frequency by two, improving transient response while operating each channel at an optimum frequency for efficiency. thermal design is also simplified. an internal differential amplifier provides true remote sensing of the regulated supplys positive and negative output terminals as required for high current applications. the run/ss pin provides soft-start and optional timed, short-circuit shutdown. current foldback limits mosfet dissipation during short-circuit conditions when the overcurrent latchoff is disabled. opti-loop compensa- tion allows the transient response to be optimized for a wide range of output capacitors and esr values. the ltc1709-8/ltc1709-9 implement two different vid tables compliant with vrm8.4 and vrm9.0 respectively. figure 1. high current 2-phase step-down converter n workstations n internet servers n large memory arrays n dc power distribution systems n single controller operates two output stages antiphase reducing required input capacitance and power supply induced noise n two 5-bit desktop vid codes: ltc1709-8 for vrm8.4 (v out from 1.3v to 3.5v) ltc1709-9 for vrm9.0 (v out from 1.1v to 1.85v) n current mode control ensures best current sharing n true remote sensing differential amplifier n power good output indicator n opti-loop tm compensation minimizes c out n programmable fixed frequency: 150khz to 300khz n 1% output voltage accuracy n wide v in range: 4v to 36v operation n adjustable soft-start current ramping n internal current foldback and short-circuit shutdown n overvoltage soft latch eliminates nuisance trips n low shutdown current: 20 m a n available in 36-lead narrow ssop package 17097 f01 tg1 boost1 sw1 bg1 pgnd sense1 + sense1 tg2 boost2 sw2 bg2 intv cc sense2 + sense2 v in run/ss v diffout i th attenin attenout eain vid0?id4 v os v os + ltc1709-8 sgnd pgood 0.1 f 220pf 5 vid bits s s 3.3k + 10 f 35v 4 + + c out 1000 f 4v 2 v out 1.3v to 3.5v 40a 1 h 0.002 0.002 v in 5v to 28v 1 h 0.47 f 0.47 f 10 f 2-phase, 5-bit vid, current mode, high efficiency, synchronous step-down switching regulators
2 ltc1709-8/ltc1709-9 order part number ltc1709eg-8 ltc1709eg-9 absolute axi u rati gs w ww u package/order i for atio uu w t jmax = 125 c, q ja = 90 c/w consult factory for industrial and military grade parts. electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 15v, v bias = 5v, v run/ss = 5v unless otherwise noted. (note 1) input supply voltage (v in ).........................36v to C 0.3v topside driver voltages (boost1,2) .........42v to C 0.3v switch voltage (sw1, 2) ..............................36v to C 5v sense1 + , sense2 + , sense1 C , sense2 C voltages ........................ (1.1)intv cc to C 0.3v eain, v os + , v os C , extv cc , intv cc , run/ss, v bias , attenin, attenout, pgood, vid0Cvid4, voltages ...................................7v to C 0.3v boosted driver voltage (boost-sw) .......... 7v to C 0.3v pllfltr, pllin, v diffout voltages .... intv cc to C 0.3v i th voltage ................................................2.7v to C 0.3v peak output current <1 m s(tgl1,2, bg1,2) ................ 3a intv cc rms output current ................................ 50ma operating ambient temperature range (note 2) ................................................ C 40 c to 85 c junction temperature (note 3) ............................. 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c symbol parameter conditions min typ max units main control loop v eain regulated feedback voltage i th voltage = 1.2v (note 4) l 0.792 0.800 0.808 v v sensemax maximum current sense threshold v sense C = 5v l 62 75 88 mv i ineain feedback current (note 4) C 5 C 50 na v loadreg output voltage load regulation (note 4) measured in servo loop, d i th voltage: 1.2v to 0.7v l 0.1 0.5 % measured in servo loop, d i th voltage: 1.2v to 2v l C 0.1 C 0.5 % v reflnreg reference voltage line regulation v in = 3.6v to 30v (note 4) 0.002 0.02 %/v v ovl output overvoltage threshold measured at v eain l 0.84 0.86 0.88 v uvlo undervoltage lockout v in ramping down 3 3.5 4 v g m transconductance amplifier g m i th = 1.2v, sink/source 5 m a (note 4) 3 mmho g mol transconductance amplifier gain i th = 1.2v, (g m xz l ; no ext load) (note 4) 1.5 v/mv i q input dc supply current (note 5) normal mode extv cc tied to v out , v out = 5v 470 m a shutdown v run/ss = 0v 20 40 m a i run/ss soft-start charge current v run/ss = 1.9v C 0.5 C1.2 m a v run/ss run/ss pin on arming v run/ss rising 1.0 1.5 1.9 v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 top view g package 36-lead plastic ssop 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 runn/ss sense1 + sense1 eain pllfltr pllin nc i th sgnd v diffout v os v os + sense2 sense2 + attenout attenin vid0 vid1 nc tg1 sw1 boost1 v in bg1 extv cc intv cc pgnd bg2 boost2 sw2 tg2 pgood v bias vid4 vid3 vid2 3 ltc1709-8/ltc1709-9 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 15v, v bias = 5v, v run/ss = 5v unless otherwise noted. symbol parameter conditions min typ max units v run/sslo run/ss pin latchoff arming v run/ss rising from 3v 4.1 4.5 v i scl run/ss discharge current soft short condition v eain = 0.5v, v run/ss = 4.5v 0.5 2 4 m a i sdlho shutdown latch disable current v eain = 0.5v 1.6 5 m a i sense total sense pins source current each channel: v sense1 C , 2 C = v sense1 + , 2 + = 0v C 85 C 60 m a df max maximum duty factor in dropout 98 99.5 % top gate transition time: (note 6) tg1, 2 t r rise time c load = 3300pf 30 90 ns tg1, 2 t f fall time c load = 3300pf 40 90 ns bottom gate transition time: (note 6) bg1, 2 t r rise time c load = 3300pf 30 90 ns bg1, 2 t f fall time c load = 3300pf 20 90 ns tg/bg t 1d top gate off to bottom gate on delay c load = 3300pf each driver (note 6) 90 ns synchronous switch-on delay time bg/tg t 2d bottom gate off to top gate on delay c load = 3300pf each driver (note 6) 90 ns top switch-on delay time t on(min) minimum on-time tested with a square wave (note 7) 180 ns internal v cc regulator v intvcc internal v cc voltage 6v < v in < 30v, v extvcc = 4v 4.8 5.0 5.2 v v ldo int intv cc load regulation i cc = 0 to 20ma, v extvcc = 4v 0.2 1.0 % v ldo ext extv cc voltage drop i cc = 20ma, v extvcc = 5v 80 160 mv v extvcc extv cc switchover voltage i cc = 20ma, extv cc ramping positive l 4.5 4.7 v v ldohys extv cc switchover hysteresis i cc = 20ma, extv cc ramping negative 0.2 v vid parameters v bias operating supply voltage range 2.7 5.5 v r atten resistance between attenin ltc1709-8 20 k w and attenout pins ltc1709-9 10 k w atten err resistive divider error ltc1709-8: vid4 = 0; ltc1709-9 l C 0.25 0.25 % ltc1709-8: vid4 = 1 l C0.35 0.25 % r pullup vid0Cvid4 pull-up resistance (note 8) 40 k w vid thlow vid0Cvid4 logic threshold low 0.4 v vid thhigh vid0Cvid4 logic threshold high 1.6 v vid leak vid0Cvid4 leakage v bias < vid0Cvid4 < 7v 0.1 1 m a oscillator and phase-locked loop f nom nominal frequency v pllfltr = 1.2v 190 220 250 khz f low lowest frequency v pllfltr = 0v 120 140 160 khz f high highest frequency v pllfltr 3 2.4v 280 320 360 khz r pllin pllin input resistance 50 k w i pllfltr phase detector output current sinking capability f pllin < f osc C15 m a sourcing capability f pllin > f osc 15 m a r relphs controller 2-controller 1 phase 180 deg 4 ltc1709-8/ltc1709-9 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 15v, v run/ss = 5v unless otherwise noted. note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 7: the minimum on-time condition corresponds to the on inductor peak-to-peak ripple current 3 40% i max (see minimum on-time considerations in the applications information section). note 8: each built-in pull-up resistor attached to the vid inputs also has a series diode to allow input voltages higher than the vidv cc supply without damage or clamping (see the applications information section). note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the ltc1709eg is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C 40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: ltc1709eg: t j = t a + (p d ? 85 c/w) note 4: the ltc1709-8/ltc1709-9 are tested in a feedback loop that servos v ith to a specified voltage and measures the resultant v eain . typical perfor a ce characteristics uw efficiency vs output current (figure 12) output current (a) 0.1 efficiency (%) 100 80 60 40 20 0 170989 g01 1 10 100 v out = 2v v extvcc = 0v freq = 200khz v in = 5v v in = 8v v in = 12v v in = 20v efficiency vs output current (figure 12) v in (v) 5 efficiency (%) 100 90 80 70 170989 g03 10 15 20 v out = 3.3v v extvcc = 5v i out = 20a efficiency vs output current (figure 12) symbol parameter conditions min typ max units pgood output v pgl pgood voltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v 1 m a v pg pgood trip level, either controller v eain with respect to set output voltage v eain ramping negative C 6 C 7.5 C 9.5 % v eain ramping positive 6 7.5 9.5 % differential amplifier/op amp gain block a da gain 0.995 1 1.005 v/v cmrr da common mode rejection ratio 0v < v cm < 5v 46 55 db r in input resistance measured at v os + input 80 k w output current (a) 0.1 efficiency (%) 40 60 170989 g02 20 0 10 1 100 100 80 v in = 12v v out = 2v freq = 200khz v extvcc = 5v v extvcc = 0v 5 ltc1709-8/ltc1709-9 typical perfor a ce characteristics uw supply current vs input voltage and mode (figure 12) extv cc voltage drop intv cc and extv cc switch voltage vs temperature input voltage (v) 05 0 supply current ( a) 400 1000 10 20 25 170989 g04 200 800 600 15 30 35 on shutdown current (ma) 0 extv cc voltage drop (mv) 150 200 250 40 170989 g05 100 50 0 10 20 30 50 temperature ( c) ?0 intv cc and extv cc switch voltage (v) 4.95 5.00 5.05 25 75 170989 g06 4.90 4.85 ?5 0 50 100 125 4.80 4.70 4.75 intv cc voltage extv cc switchover threshold maximum current sense threshold vs percent of nominal output voltage (foldback) internal 5v ldo line regulation maximum current sense threshold vs duty factor input voltage (v) 0 4.8 4.9 5.1 15 25 170989 g07 4.7 4.6 510 20 30 35 4.5 4.4 5.0 intv cc voltage (v) i load = 1ma duty factor (%) 0 0 v sense (mv) 25 50 75 20 40 60 80 170989 g08 100 percent on nominal output voltage (%) 0 v sense (mv) 40 50 60 100 170989 g09 30 20 0 25 50 75 10 80 70 maximum current sense threshold vs v run/ss (soft-start) maximum current sense threshold vs sense common mode voltage current sense threshold vs i th voltage v run/ss (v) 0 0 v sense (mv) 20 40 60 80 1234 170989 g10 56 v sense(cm) = 1.6v common mode voltage (v) 0 v sense (mv) 72 76 80 4 170989 g11 68 64 60 1 2 3 5 v ith (v) 0 v sense (mv) 30 50 70 90 2 170989 g12 10 ?0 20 40 60 80 0 ?0 ?0 0.5 1 1.5 2.5 6 ltc1709-8/ltc1709-9 typical perfor a ce characteristics uw load regulation v ith vs v run/ss sense pins total source current load current (a) 0 normalized v out (%) 0.2 0.1 4 1629 g13 0.3 0.4 1 2 3 5 0.0 fcb = 0v v in = 15v figure 1 v run/ss (v) 0 0 v ith (v) 0.5 1.0 1.5 2.0 2.5 1 234 1629 g14 56 v osense = 0.7v v sense common mode voltage (v) 0 i sense ( a) 0 1629 g15 ?0 100 24 50 100 6 maximum current sense threshold vs temperature temperature ( c) 50 ?5 70 v sense (mv) 74 80 0 50 75 170989 g16 72 78 76 25 100 125 run/ss current vs temperature temperature ( c) ?0 25 0 run/ss current ( a) 0.2 0.6 0.8 1.0 75 100 50 1.8 170989 g17 0.4 0 25 125 1.2 1.4 1.6 soft-start (figure 12) load step (figure 12) v ith 1v/div v out 2v/div v run/ss 2v/div 100ms/div 170989 g18 i out 0/20a v out 50mv/div 20 m s/div 170989 g19 7 ltc1709-8/ltc1709-9 typical perfor a ce characteristics uw current sense pin input current vs temperature extv cc switch resistance vs temperature oscillator frequency vs temperature temperature ( c) ?0 25 25 current sense input current ( a) 29 35 0 50 75 170989 g20 27 33 31 25 100 125 v out = 5v temperature ( c) ?0 25 0 extv cc switch resistance ( ) 4 10 0 50 75 170989 g21 2 8 6 25 100 125 temperature ( c) ?0 200 250 350 25 75 170989 g22 150 100 ?5 0 50 100 125 50 0 300 frequency (khz) v freqset = 5v v freqset = open v freqset = 0v undervoltage lockout vs temperature temperature ( c) ?0 undervoltage lockout (v) 3.40 3.45 3.50 25 75 170989 g23 3.35 3.30 ?5 0 50 100 125 3.25 3.20 shutdown latch thresholds vs temperature temperature ( c) ?0 25 0 shutdown latch thresholds (v) 0.5 1.5 2.0 2.5 75 100 50 4.5 170989 g24 1.0 0 25 125 3.0 3.5 4.0 latch arming latchoff threshold run/ss (pin 1): combination of soft-start, run control input and short-circuit detection timer. a capacitor to ground at this pin sets the ramp time to full current output. forcing this pin below 0.8v causes the ic to shut down all internal circuitry. all functions are disabled in shutdown. sense1 + , sense2 + (pins 2,14): the (+) input to each differential current comparator. the i th pin voltage and built-in offsets between sense C and sense + pins in conjunction with r sense set the current trip threshold. pi fu ctio s uuu sense1 C , sense2 C (pins 3, 13): the (C) input to the differential current comparators. eain (pin 4): input to the error amplifier that compares the feedback voltage to the internal 0.8v reference voltage. this pin is normally connected to a resistive divider from the output of the differential amplifier (diffout). pllfltr (pin 5): the phase-locked loops lowpass filter is tied to this pin. alternatively, this pin can be driven with an ac or dc voltage source to vary the frequency of the internal oscillator. 8 ltc1709-8/ltc1709-9 pi fu ctio s uuu tg2, tg1 (pins 24, 35): high current gate drives for top n-channel mosfets. these are the outputs of floating drivers with a voltage swing equal to intv cc superim- posed on the switch node voltage sw. sw2, sw1 (pins 25, 34): switch node connections to inductors. voltage swing at these pins is from a schottky diode (external) voltage drop below ground to v in . boost2, boost1 (pins 26, 33): bootstrapped supplies to the topside floating drivers. external capacitors are connected between the boost and sw pins, and schottky diodes are connected between the boost and intv cc pins. bg2, bg1 (pins 27, 31): high current gate drives for bottom n-channel mosfets. voltage swing at these pins is from ground to intv cc . pgnd (pin 28): driver power ground. connect to sources of bottom n-channel mosfets and the (C) terminals of c in . intv cc (pin 29): output of the internal 5v linear low dropout regulator and the extv cc switch. the driver and control circuits are powered from this voltage source. decouple to power ground with a 1 m f ceramic capacitor placed directly adjacent to the ic and minimum of 4.7 m f additional tantalum or other low esr capacitor. extv cc (pin 30): external power input to an internal switch. this switch closes and supplies intv cc, bypass- ing the internal low dropout regulator whenever extv cc is higher than 4.7v. see extv cc connection in the applica- tions information section. do not exceed 7v on this pin and ensure v extvcc v in . v in (pin 32): main supply pin. should be closely de- coupled to the ics signal ground pin. pllin (pin 6): external synchronization input to phase detector. this pin is internally terminated to sgnd with 50k w . the phase-locked loop will force the rising top gate signal of controller 1 to be synchronized with the rising edge of the pllin signal. nc (pins 7, 36): do not connect. i th (pin 8): error amplifier output and switching regula- tor compensation point. both current comparators thresh- olds increase with this control voltage. the normal voltage range of this pin is from 0v to 2.4v sgnd (pin 9): signal ground. this pin is common to both controllers. route separately to the pgnd pin. v diffout (pin 10): output of a differential amplifier. this pin provides true remote output voltage sensing. v diffout normally drives an external resistive divider that sets the output voltage. v os C , v os + (pins 11, 12): inputs to an operational ampli- fier. internal precision resistors capable of being elec- tronically switched in or out can configure it as a differential amplifier or an uncommitted op amp. attenout (pin 15): voltage feedback signal resistively divided according to the vid programming code. attenin (pin 16): the input to the vid controlled resis- tive divider. vid0Cvid4 (pins 17,18, 19, 20, 21): vid control logic input pins. v bias (pin 22): supply pin for the vid control circuit. pgood (pin 23): open-drain logic output. pgood is pulled to ground when the voltage on the eain pin is not within 7.5% of its set point. 9 ltc1709-8/ltc1709-9 fu ctio al diagra uu w switch logic 0.80v 4.7v 5v v in v in clk2 clk1 + + v ref internal supply extv cc intv cc sgnd + 5v ldo reg sw shdn top boost tg c b c in d b pgnd bot bg intv cc intv cc v in + v out 170989 fbd eain drop out det run soft start bot force bot s r q q oscillator pllfltr 50k ea 0.86v 0.80v ov 1.2 a 6v + r c 4(v fb ) rst shdn run/ss i th c c c ss 4(v fb ) 0.86v slope comp + sense sense + intv cc 30k 45k 2.4v 45k 30k i 1 attenin 20k (ltc1709-8) 10k (ltc1709-9) r1 vid0 attenout vid1 vid2 vid3 vid4 typical all vid pins 40k v bias phase det pllin duplicate for second controller channel + r sense l c out + f in r lp c lp a1 + diffout v os + v os 0.74v 0.86v + + eain pgood 5-bit vid decoder rr rr 10 ltc1709-8/ltc1709-9 operatio u (refer to functional diagram) main control loop the ltc1709 uses a constant frequency, current mode step-down architecture with inherent current sharing. during normal operation, the top mosfet is turned on each cycle when the oscillator sets the rs latch, and turned off when the main current comparator, i 1 , resets the rs latch. the peak inductor current at which i 1 resets the rs latch is controlled by the voltage on the i th pin, which is the output of the error amplifier ea. the differen- tial amplifier, a1, produces a signal equal to the differen- tial voltage sensed across the output capacitor but re-references it to the internal signal ground (sgnd) reference. the eain pin receives a portion of this voltage feedback signal at the diffout as determined by vid logic input pins (vid0 to vid4) and is compared to the internal reference voltage by the ea. when the load current increases, it causes a slight decrease in the eain pin voltage relative to the 0.8v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. after the top mosfet has turned off, the bottom mosfet is turned on for the rest of the period. the top mosfet drivers are biased from floating boot- strap capacitor c b , which normally is recharged during each off cycle through an external schottky diode. when v in decreases to a voltage close to v out , however, the loop may enter dropout and attempt to turn on the top mosfet continuously. a dropout detector detects this condition and forces the top mosfet to turn off for about 400ns every 10th cycle to recharge the bootstrap capacitor, c b . the main control loop is shut down by pulling pin 1 (run/ ss) low. releasing run/ss allows an internal 1.2 m a current source to charge soft-start capacitor c ss . when c ss reaches 1.5v, the main control loop is enabled with the i th voltage clamped at approximately 30% of its maximum value. as c ss continues to charge, i th is gradually released allowing normal operation to resume. when the run/ss pin is low, all ltc1709 functions are shut down. if v out has not reached 70% of its nominal value when c ss has charged to 4.1v, an overcurrent latchoff can be invoked as described in the applications information section. low current operation the ltc1709 operates in a continuous, pwm control mode. the resulting operation at low output currents optimizes transient response at the expense of substantial negative inductor current during the latter part of the period. the level of ripple current is determined by the inductor value, input voltage, output voltage and fre- quency of operation. frequency synchronization the phase-locked loop allows the internal oscillator to be synchronized to an external source via the pllin pin. the output of the phase detector at the pllfltr pin is also the dc frequency control input of the oscillator that operates over a 140khz to 310khz range corresponding to a dc voltage input from 0v to 2.4v. when locked, the pll aligns the turn on of the top mosfet to the rising edge of the synchronizing signal. when pllin is left open, the pllfltr pin goes low, forcing the oscillator to minimum frequency. input capacitance esr requirements and efficiency losses are substantially reduced because the peak current drawn from the input capacitor is effectively divided by two and power loss is proportional to the rms current squared. a two stage, single output voltage implementation can reduce input path power loss by 75% and radically reduce the required rms current rating of the input capacitor(s). intv cc /extv cc power power for the top and bottom mosfet drivers and most of the ic circuitry is derived from intv cc . when the extv cc pin is left open, an internal 5v low dropout regulator supplies intv cc power. if the extv cc pin is taken above 4.7v, the 5v regulator is turned off and an internal switch is turned on connecting extv cc to intv cc . this allows the intv cc power to be derived from a high efficiency external source such as the output of the regu- lator itself or a secondary winding, as described in the applications information section. an external schottky diode can be used to minimize the voltage drop from extv cc to intv cc in applications requiring greater than the specified intv cc current. voltages up to 7v can be applied to extv cc for additional gate drive capability. 11 ltc1709-8/ltc1709-9 operatio u (refer to functional diagram) differential amplifier this amplifier provides true differential output voltage sensing. sensing both v out + and v out C benefits regula- tion in high current applications and/or applications hav- ing electrical interconnection losses. the ampmd pin allows selection of internal, precision feedback resistors for high common mode rejection differencing applica- tions, or direct access to the actual amplifier inputs without these internal feedback resistors for other applica- tions. the ampmd pin is grounded to connect the internal precision resistors in a unity-gain differencing application, or tied to the intv cc pin to bypass the internal resistors and make the amplifier inputs directly available. the amplifier is a unity-gain stable, 2mhz gain bandwidth, >120db open-loop gain design. the amplifier has an output slew rate of 5v/ m s and is capable of driving capaci- tive loads with an output rms current typically up to 35ma. the amplifier is not capable of sinking current and therefore must be resistively loaded to do so. power good (pgood) the pgood pin is connected to the drain of an internal mosfet. the mosfet turns on when the output voltage is not within 7.5% of its nominal output level as deter- mined by the feedback divider. when the output is within 7.5% of its nominal value, the mosfet is turned off within 10 m s and the pgood pin should be pulled up by an external resistor to a source of up to 7v. short-circuit detection the run/ss capacitor is used initially to limit the inrush current from the input power source. once the controllers have been given time, as determined by the capacitor on the run/ss pin, to charge up the output capacitors and provide full-load current, the run/ss capacitor is then used as a short-circuit timeout circuit. if the output voltage falls to less than 70% of its nominal output voltage the run/ss capacitor begins discharging assuming that the output is in a severe overcurrent and/or short-circuit condition. if the condition lasts for a long enough period as determined by the size of the run/ss capacitor, the controller will be shut down until the run/ss pin voltage is recycled. this built-in latchoff can be overidden by providing a current >5 m a at a compliance of 5v to the run/ss pin. this current shortens the soft-start period but also prevents net discharge of the run/ss capacitor during a severe overcurrent and/or short-circuit condi- tion. foldback current limiting is activated when the output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled. applicatio s i for atio wu u u the basic ltc1709 application circuit is shown in fig- ure 1 on the first page. external component selection begins with the selection of the inductor(s) based on ripple current requirements and continues with the r sense1, 2 resistor selection using the calculated peak inductor current and/or maximum current limit. next, the power mosfets and d1 and d2 are selected. the oper- ating frequency and the inductor are chosen based mainly on the amount of ripple current. finally, c in is selected for its ability to handle the input ripple current (that polyphase tm operation minimizes) and c out is chosen with low enough esr to meet the output ripple voltage and load step specifications (also minimized with polyphase). current mode architecture provides inherent current sharing between output stages. the circuit shown in figure 1 can be configured for operation up to an input voltage of 28v (limited by the external mosfets). r sense selection for output current r sense1, 2 are chosen based on the required peak output current. the ltc1709 current comparator has a maxi- mum threshold of 75mv/r sense and an input common mode range of sgnd to 1.1(intv cc ). the current com- parator threshold sets the peak inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to-peak ripple current, d i l . polyphase is a trademark of linear technology corporation. 12 ltc1709-8/ltc1709-9 applicatio s i for atio wu u u allowing a margin for variations in the ltc1709 and external component values yields: r sense = 2(50mv/i max ) operating frequency the ltc1709 uses a constant frequency, phase-lockable architecture with the frequency determined by an internal capacitor. this capacitor is charged by a fixed current plus an additional current which is proportional to the voltage applied to the pllfltr pin. refer to phase- locked loop and frequency synchronization for addi- tional information. a graph for the voltage applied to the pllfltr pin vs frequency is given in figure 2. as the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see efficiency considerations). the maximum switching frequency is approximately 310khz. effect of inductor value on ripple current and low current operation must also be considered. the polyphase ap- proach reduces both input and output ripple currents while optimizing individual output stages to run at a lower fundamental frequency, enhancing efficiency. the inductor value has a direct effect on ripple current. the inductor ripple current d i l per individual section, n, decreases with higher inductance or frequency and increases with higher v in or v out : d i v fl v v l out out in =- ? ? ? ? 1 where f is the individual output stage operating frequency. in a 2-phase converter, the net ripple current seen by the output capacitor is much smaller than the individual inductor ripple currents due to ripple cancellation. the details on how to calculate the net output ripple current can be found in application note 77. figure 3 shows the net ripple current seen by the output capacitors for the 1- and 2- phase configurations. the output ripple current is plotted for a fixed output voltage as the duty factor is varied between 10% and 90% on the x-axis. the output ripple current is normalized against the inductor ripple current at zero duty factor. the graph can be used in place of tedious calculations, simplifying the design process. figure 2. operating frequency vs v pllfltr operating frequency (khz) 120 170 220 270 320 pllfltr pin voltage (v) 1709 f02 2.5 2.0 1.5 1.0 0.5 0 figure 3. normalized output ripple current vs duty factor [i rms ? 0.3 ( d i o(pCp) )] inductor value calculation and output ripple current the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. so why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficiency. a higher frequency generally results in lower efficiency because mosfet gate charge and transition losses increase di- rectly with frequency. in addition to this basic tradeoff, the duty factor (v out /v in ) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1709 f03 2-phase 1-phase ? i o(p-p) v o /fl 13 ltc1709-8/ltc1709-9 accepting larger values of d i l allows the use of low inductances, but can result in higher output voltage ripple. a reasonable starting point for setting ripple current is d i l = 0.4(i out )/2, where i out is the total load current. remem- ber, the maximum d i l occurs at the maximum input voltage. the individual inductor ripple currents are deter- mined by the inductor, input and output voltages. inductor core selection once the values for l1 and l2 are known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or kool m m ? cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as induc- tance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! molypermalloy (from magnetics, inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. a reasonable compromise from the same manufacturer is kool m m . toroids are very space effi- cient, especially when you can use several layers of wire. because they lack a bobbin, mounting is more difficult. however, designs for surface mount are available which do not increase the height significantly. power mosfet, d1 and d2 selection two external power mosfets must be selected for each controller with the ltc1709: one n-channel mosfet for the top (main) switch, and one n-channel mosfet for the bottom (synchronous) switch. the peak-to-peak drive levels are set by the intv cc voltage. this voltage is typically 5v during start-up (see extv cc pin connection). consequently, logic-level threshold mosfets must be used in most applications. the only exception is if low input voltage is expected (v in < 5v); then, sublogic-level threshold mosfets (v gs(th) < 1v) should be used. pay close attention to the bv dss specification for the mosfets as well; most of the logic-level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on resistance r ds(on) , reverse transfer capacitance c rss , input voltage and maximum output current. when the ltc1709 is operating in continuous mode the duty factors for the top and bottom mosfets of each output stage are given by: main switch duty cycle v v out in = synchronous switch duty cycle vv v in out in = ? ? ? ? the mosfet power dissipations at maximum output current are given by: p v v i r kv i cf main out in max ds on in max rss = ? ? ? ? + () + () ? ? ? ? ()() 2 1 2 2 2 d () p vv v i r sync in out in max ds on = ? ? ? ? + () () 2 1 2 d where d is the temperature dependency of r ds(on) and k is a constant inversely related to the gate drive current. both mosfets have i 2 r losses but the topside n-channel equation includes an additional term for transition losses, which peak at the highest input voltage. for v in < 20v the high current efficiency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c rss actual provides higher efficiency. the applicatio s i for atio wu u u kool m m is a registered trademark of magnetics, inc. 14 ltc1709-8/ltc1709-9 synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1 + d ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d = 0.005/ c can be used as an approximation for low voltage mosfets. c rss is usually specified in the mosfet characteristics. the constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. the schottky diodes, d1 and d2 shown in figure 1 conduct during the dead-time between the conduction of the two large power mosfets. this helps prevent the body diode of the bottom mosfet from turning on, storing charge during the dead-time, and requiring a reverse recovery period which would reduce efficiency. a 1a to 3a schottky (depending on output current) diode is generally a good compromise for both regions of opera- tion due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. c in and c out selection in continuous mode, the source current of each top n-channel mosfet is a square wave of duty cycle v out / v in . a low esr input capacitor sized for the maximum rms current must be used. the details of a closed form equation can be found in application note 77. figure 4 shows the input capacitor ripple current for a 2-phase configuration with the output voltage fixed and input voltage varied. the input ripple current is normalized against the dc output current. the graph can be used in place of tedious calculations. the minimum input ripple current can be achieved when the input voltage is twice the output voltage in the graph of figure 4, the 2-phase local maximum input rms capacitor currents are reached when: v v k out in = - 21 4 where k = 1, 2 these worst-case conditions are commonly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the capacitor manufacturer if there is any question. it is important to note that the efficiency loss is propor- tional to the input rms current squared and therefore a 2-phase implementation results in 75% less power loss when compared to a single phase design. battery/input protection fuse resistance (if used), pc board trace and connector resistance losses are also reduced by the reduction of the input ripple current in a 2-phase system. the required amount of input capacitance is further reduced by the factor, 2, due to the effective increase in the frequency of the current pulses. the selection of c out is driven by the required effective series resistance (esr). typically once the esr require- ment has been met, the rms current rating generally far exceeds the i ripple(p-p) requirements. the steady state output ripple ( d v out ) is determined by: dd v i esr fc out ripple out ?+ ? ? ? ? 1 16 applicatio s i for atio wu u u figure 4. normalized rms input ripple current vs duty factor for 1 and 2 output stages duty factor (v out /v in ) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.6 0.5 0.4 0.3 0.2 0.1 0 170989 f04 rms input ripple currnet dc load current 2-phase 1-phase 15 ltc1709-8/ltc1709-9 where f = operating frequency of each stage, c out = output capacitance and d i ripple = combined inductor ripple currents. the output ripple varies with input voltage since d i l is a function of input voltage. the output ripple will be less than 50mv at max v in with d i l = 0.4i out(max) /2 assuming: c out required esr < 4(r sense ) and c out > 1/(16f)(r sense ) the emergence of very low esr capacitors in small, surface mount packages makes very physically small implementations possible. the ability to externally com- pensate the switching regulator loop using the i th pin(opti-loop compensation) allows a much wider se- lection of output capacitor types. opti-loop compensa- tion effectively removes constraints on output capacitor esr. the impedance characteristics of each capacitor type are significantly different than an ideal capacitor and therefore require accurate modeling or bench evaluation during design. manufacturers such as nichicon, united chemicon and sanyo should be considered for high performance through-hole capacitors. the os-con semiconductor dielectric capacitor available from sanyo and the panasonic sp surface mount types have the lowest (esr)(size) product of any aluminum electrolytic at a somewhat higher price. an additional ceramic capacitor in parallel with os-con type capacitors is recommended to reduce the inductance effects. in surface mount applications, multiple capacitors may have to be paralleled to meet the esr or rms current handling requirements of the application. aluminum elec- trolytic and dry tantalum capacitors are both available in surface mount configurations. new special polymer sur- face mount capacitors offer very low esr also but have much lower capacitive density per unit volume. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. several excellent choices are the avx tps, avx tpsv or the kemet t510 series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. other capacitor types include sanyo os-con, nichicon pl series and sprague 595d series. consult the manufacturer for other specific recom- mendations. a combination of capacitors will often result in maximizing performance and minimizing overall cost and size. intv cc regulator an internal p-channel low dropout regulator produces 5v at the intv cc pin from the v in supply pin. the intv cc regulator powers the drivers and internal circuitry of the ltc1709. the intv cc pin regulator can supply up to 50ma peak and must be bypassed to power ground with a minimum of 4.7 m f tantalum or electrolytic capacitor. an additional 1 m f ceramic capacitor placed very close to the ic is recommended due to the extremely high instanta- neous currents required by the mosfet gate drivers. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi- mum junction temperature rating for the ltc1709 to be exceeded. the supply current is dominated by the gate charge supply current, in addition to the current drawn from the differential amplifier output. the gate charge is dependent on operating frequency as discussed in the efficiency considerations section. the supply current can either be supplied by the internal 5v regulator or via the extv cc pin. when the voltage applied to the extv cc pin is less than 4.7v, all of the intv cc load current is supplied by the internal 5v linear regulator. power dissipation for the ic is higher in this case by (i in )(v in C intv cc ) and efficiency is lowered. the junction temperature can be estimated by using the equations given in note 1 of the electrical characteristics. for example, the ltc1709 v in current is limited to less than 24ma from a 24v supply: t j = 70 c + (24ma)(24v)(85 c/w) = 119 c use of the extv cc pin reduces the junction temperature to: t j = 70 c + (24ma)(5v)(85 c/w) = 80.2 c the input supply current should be measured while the controller is operating in continuous mode at maximum v in and the power dissipation calculated in order to prevent the maximum junction temperature from being exceeded. applicatio s i for atio wu u u 16 ltc1709-8/ltc1709-9 figure 5a. secondary output loop with extv cc connection figure 5b. capacitive charge pump for extv cc extv cc connection the ltc1709 contains an internal p-channel mosfet switch connected between the extv cc and intv cc pins. when the voltage applied to extv cc rises above 4.7v, the internal regulator is turned off and an internal switch closes, connecting the extv cc pin to the intv cc pin thereby supplying internal and mosfet gate driving power to the ic. the switch remains closed as long as the voltage applied to extv cc remains above 4.5v. this allows the mosfet driver and control power to be derived from the output during normal operation (4.7v < v extvcc < 7v) and from the internal regulator when the output is out of regulation (start-up, short-circuit). do not apply greater than 7v to the extv cc pin and ensure that extv cc < v in + 0.3v when using the application circuits shown. if an external voltage source is applied to the extv cc pin when the v in supply is not present, a diode can be placed in series with the ltc1709s v in pin and a schottky diode between the extv cc and the v in pin, to prevent current from backfeeding v in . significant efficiency gains can be realized by powering intv cc from the output, since the v in current resulting from the driver and control currents will be scaled by the ratio: (duty factor)/(efficiency). for 5v regulators this means connecting the extv cc pin directly to v out . how- ever, for 3.3v and other lower voltage regulators, addi- tional circuitry is required to derive intv cc power from the output. the following list summarizes the four possible connec- tions for extv cc: 1. extv cc left open (or grounded). this will cause intv cc to be powered from the internal 5v regulator resulting in a significant efficiency penalty at high input voltages. 2. extv cc connected directly to v out . this is the normal connection for a 5v regulator and provides the highest efficiency. 3. extv cc connected to an external supply. if an external supply is available in the 5v to 7v range, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. 4. extv cc connected to an output-derived boost network. for 3.3v and other low voltage regulators, efficiency gains can still be realized by connecting extv cc to an output- derived voltage which has been boosted to greater than 4.7v but less than 7v. this can be done with either the inductive boost winding as shown in figure 5a or the capacitive charge pump shown in figure 5b. the charge pump has the advantage of simple magnetics. topside mosfet driver supply (c b ,d b ) (refer to functional diagram) external bootstrap capacitors c b1 and c b2 connected to the boost1 and boost2 pins supply the gate drive voltages for the topside mosfets. capacitor c b in the functional diagram is charged though diode d b from applicatio s i for atio wu u u 1709 f05a v in tg1 n-ch 1n4148 n-ch bg1 pgnd ltc1709 sw1 extv cc optional extv cc connection 5v < v sec < 7v t1 r sense v sec v out v in + c in + 1 f + c out 1709 f05b v in tg1 n-ch n-ch bg1 pgnd ltc1709 sw1 extv cc l1 r sense bat85 bat85 bat85 0.22 f v out v in + c in + + c out vn2222ll 17 ltc1709-8/ltc1709-9 intv cc when the sw pin is low. when the topside mosfet turns on, the driver places the c b voltage across the gate- source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin rises to v in + v intvcc . the value of the boost capacitor c b needs to be 30 to 100 times that of the total input capacitance of the topside mosfet(s). the reverse breakdown of d b must be greater than v in(max). the final arbiter when defining the best gate drive ampli- tude level will be the input supply current. if a change is made that decreases input current, the efficiency has improved. if the input current does not change then the efficiency has not changed either. output voltage the ltc1709 has a true remote voltage sense capablity. the sensing connections should be returned from the load back to the differential amplifiers inputs through a com- mon, tightly coupled pair of pc traces. the differential amplifier corrects for dc drops in both the power and ground paths. the differential amplifier output signal is divided down and compared with the internal precision 0.8v voltage reference by the error amplifier. output voltage programming the output voltage is digitally programmed as defined in table 1 using the vid0 to vid4 logic input pins. the vid logic inputs program a precision, 0.25% internal feedback resistive divider. the ltc1709-8 has an output voltage range of 1.30v to 3.5v in 50mv and 100mv steps. the ltc1709-9 has an output voltage range of 1.10v to 1.85v in 25mv steps. between the attenout pin and ground is a variable resistor, r1, whose value is controlled by the five vid input pins (vid0 to vid4). another resistor, r2, between the attenin and the attenout pins completes the resistive divider. the output voltage is thus set by the ratio of (r1 + r2) to r1. applicatio s i for atio wu u u table 1. vid output voltage programming ltc1709-8 ltc1709-9 vid4 vid3 vid2 vid1 vid0 vrm8.4 vrm9.0 00000 2.05v 1.850v 00001 2.00v 1.825v 00010 1.95v 1.800v 00011 1.90v 1.775v 00100 1.85v 1.750v 00101 1.80v 1.725v 00110 1.75v 1.700v 00111 1.70v 1.675v 01000 1.65v 1.650v 01001 1.60v 1.625v 01010 1.55v 1.600v 01011 1.50v 1.575v 01100 1.45v 1.550v 01101 1.40v 1.525v 01110 1.35v 1.500v 01111 1.30v 1.475v 10000 3.50v 1.450v 10001 3.40v 1.425v 10010 3.30v 1.400v 10011 3.20v 1.375v 10100 3.10v 1.350v 10101 3.00v 1.325v 10110 2.90v 1.300v 10111 2.80v 1.275v 11000 2.70v 1.250v 11001 2.60v 1.225v 11010 2.50v 1.200v 11011 2.40v 1.175v 11100 2.30v 1.150v 11101 2.20v 1.125v 11110 2.10v 1.100v 11111 no_cpu/ no_cpu/ shutdown* shutdown* *represents codes without a defined output voltage as specified in intel specifications. the ltc1709 interprets these codes as a valid input and produces an output voltage as follows: ltc1709-8 (11111) = 2v ltc1709-9 (11111) = 1.075v 18 ltc1709-8/ltc1709-9 applicatio s i for atio wu u u figure 6. run/ss pin interfacing the time for the output current to ramp up is then: t vv a csfc iramp ss ss = - m =m () 315 12 125 . . ./ by pulling the run/ss pin below 0.8v the ltc1709 is put into low current shutdown (i q < 40 m a). the run/ss pins can be driven directly from logic as shown in figure 6. diode d1 in figure 6 reduces the start delay but allows c ss to ramp up slowly providing the soft-start function. the run/ss pin has an internal 6v zener clamp (see functional diagram). 3.3v or 5v run/ss v in intv cc run/ss d1 d1* c ss r ss * c ss r ss * 170989 f06 *optional to defeat overcurrent latchoff fault conditions: overcurrent latchoff the run/ss pin also provides the ability to latch off the controllers when an overcurrent condition is detected. the run/ss capacitor, c ss , is used initially to limit the inrush current of both controllers. after the controllers have been started and been given adequate time to charge up the output capacitors and provide full load current, the run/ ss capacitor is used for a short-circuit timer. if the output voltage falls to less than 70% of its nominal value after c ss reaches 4.1v, c ss begins discharging on the assumption that the output is in an overcurrent condition. if the condition lasts for a long enough period as determined by the size of the c ss , the controller will be shut down until the run/ss pin voltage is recycled. if the overload occurs during start-up, the time can be approximated by: t lo1 ? (c ss ? 0.6v)/(1.2 m a) = 5 ? 10 5 (c ss ) each vid digital input is pulled up by a 40k resistor in series with a diode from v bias . therefore, it must be grounded to get a digital low input, and can be either floated or connected to v bias to get a digital high input. the series diode is used to prevent the digital inputs from being damaged or clamped if they are driven higher than v bias . the digital inputs accept cmos voltage levels. v bias is the supply voltage for the vid section. it is normally connected to intv cc but can be driven from other sources. if it is driven from another source, that source must be in the range of 2.7v to 5.5v and must be alive prior to enabling the ltc1709. soft-start/run function the run/ss pin provides three functions: 1) run/shut- down, 2) soft-start and 3) a defeatable short-circuit latchoff timer. soft-start reduces the input power sources surge currents by gradually increasing the controllers current limit i th(max) . the latchoff timer prevents very short, extreme load transients from tripping the overcurrent latch. a small pull-up current (>5 m a) supplied to the run/ ss pin will prevent the overcurrent latch from operating. the following explanation describes how the functions operate. an internal 1.2 m a current source charges up the soft-start capacitor, c ss . when the voltage on run/ss reaches 1.5v, the controller is permitted to start operating. as the voltage on run/ss increases from 1.5v to 3.0v, the internal current limit is increased from 25mv/r sense to 75mv/r sense . the output current limit ramps up slowly, taking an additional 1.4s/ m f to reach full current. the output current thus ramps up slowly, reducing the starting surge current required from the input power supply. if run/ss has been pulled all the way to ground there is a delay before starting of approximately: t v a csfc delay ss ss = m =m () 15 12 125 . . ./ 19 ltc1709-8/ltc1709-9 of 1.2v corresponds to a frequency of approximately 220khz. the nominal operating frequency range of the ltc1709 is 140khz to 310khz. the phase detector used is an edge sensitive digital type which provides zero degrees phase shift between the external and internal oscillators. this type of phase detec- tor will not lock up on input frequencies close to the harmonics of the vco center frequency. the pll hold-in range, d f h , is equal to the capture range, d f c: d f h = d f c = 0.5 f o (150khz-300khz) the output of the phase detector is a complementary pair of current sources charging or discharging the external filter network on the pllfltr pin. a simplified block diagram is shown in figure 7. if the external frequency (f pllin ) is greater than the oscil- lator frequency f 0sc , current is sourced continuously, pulling up the pllfltr pin. when the external frequency is less than f 0sc , current is sunk continuously, pulling down the pllfltr pin. if the external and internal fre- quencies are the same but exhibit a phase difference, the current sources turn on for an amount of time correspond- ing to the phase difference. thus the voltage on the pllfltr pin is adjusted until the phase and frequency of the external and internal oscillators are identical. at this stable operating point the phase comparator output is open and the filter capacitor c lp holds the voltage. the ltc1709 pllin pin must be driven from a low impedance source such as a logic gate located close to the pin. applicatio s i for atio wu u u if the overload occurs after start-up, the voltage on c ss will continue charging and will provide additional time before latching off: t lo2 ? (c ss ? 3v)/(1.2 m a) = 2.5 ? 10 6 (c ss ) this built-in overcurrent latchoff can be overridden by providing a pull-up resistor, r ss , to the run/ss pin as shown in figure 6. this resistance shortens the soft-start period and prevents the discharge of the run/ss capaci- tor during a severe overcurrent and/or short-circuit con- dition. when deriving the 5 m a current from v in as in the figure, current latchoff is always defeated. the diode connecting this pull-up resistor to intv cc , as in figure 6, eliminates any extra supply current during shutdown while eliminating the intv cc loading from preventing controller start-up. why should you defeat current latchoff? during the prototyping stage of a design, there may be a problem with noise pickup or poor layout causing the protection circuit to latch off the controller. defeating this feature allows troubleshooting of the circuit and pc layout. the internal short-circuit and foldback current limiting still remains active, thereby protecting the power supply system from failure. a decision can be made after the design is com- plete whether to rely solely on foldback current limiting or to enable the latchoff feature by removing the pull-up resistor. the value of the soft-start capacitor c ss may need to be scaled with output voltage, output capacitance and load current characteristics. the minimum soft-start capaci- tance is given by: c ss > (c out )(v out )(10 -4 )(r sense ) the minimum recommended soft-start capacitor of c ss = 0.1 m f will be sufficient for most applications. phase-locked loop and frequency synchronization the ltc1709 has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. this allows the top mosfet turn-on to be locked to the rising edge of an external source. the frequency range of the voltage controlled oscillator is 50% around the center frequency f o . a voltage applied to the pllfltr pin figure 7. phase-locked loop block diagram external osc 2.4v r lp 10k c lp osc digital phase/ frequency detector phase detector pllin 1709 f07 pllfltr 50k 20 ltc1709-8/ltc1709-9 the loop filter components (c lp , r lp ) smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. the filter components c lp and r lp determine how fast the loop acquires lock. typically r lp =10k and c lp is 0.01 m f to 0.1 m f. minimum on-time considerations minimum on-time, t on(min) , is the smallest time duration that the ltc1709 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t v vf on min out in () < () if the duty cycle falls below what can be accommodated by the minimum on-time, the ltc1709 will begin to skip cycles resulting in variable frequency operation. the out- put voltage will continue to be regulated, but the ripple current and ripple voltage will increase. the minimum on-time for the ltc1709 is generally less than 200ns. however, as the peak sense voltage de- creases, the minimum on-time gradually increases. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with corre- spondingly larger ripple current and voltage ripple. if an application can operate close to the minimum on-time limit, an inductor must be chosen that has a low enough inductance to provide sufficient ripple amplitude to meet the minimum on-time requirement. as a general rule, keep the inductor ripple current of each phase equal to or greater than 15% of i out(max) at v in(max) . voltage positioning voltage positioning can be used to minimize peak-to-peak output voltage excursion under worst-case transient load- ing conditions. the open-loop dc gain of the control loop is reduced depending upon the maximum load step speci- fications. voltage positioning can easily be added to the ltc1709 by loading the i th pin with a resistive divider having a thevenin equivalent voltage source equal to the midpoint operating voltage of the error amplifier, or 1.2v (see figure 8). the resistive load reduces the dc loop gain while main- taining the linear control range of the error amplifier. the worst-case peak-to-peak output voltage deviation due to transient loading can theoretically be reduced to half or alternatively the amount of output capacitance can be reduced for a particular application. a complete explana- tion is included in design solutions 10 or the ltc1736 data sheet. (see www.linear-tech.com) applicatio s i for atio wu u u i th r c r t1 intv cc c c 1709 f08 ltc1709 r t2 figure 8. active voltage positioning applied to the ltc1709 efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc1709 circuits: 1) i 2 r losses, 2) topside mosfet transition losses, 3) intv cc regulator current and 4) ltc1709 v in current (including loading on the differential amplifier output). 21 ltc1709-8/ltc1709-9 1) i 2 r losses are predicted from the dc resistances of the fuse (if used), mosfet, inductor, current sense resistor, and input and output capacitor esr. in continuous mode the average output current flows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approxi- mately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l, r sense and esr to obtain i 2 r losses. for example, if each r ds(on) = 10m w , r l = 10m w , and r sense = 5m w , then the total resistance is 25m w . this results in losses ranging from 2% to 8% as the output current increases from 3a to 15a per output stage for a 5v output, or a 3% to 12% loss per output stage for a 3.3v output. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of increas- ingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 2) transition losses apply only to the topside mosfet(s), and are significant only when operating at high input voltages (typically 12v or greater). transition losses can be estimated from: transition loss = (1.7) v in 2 i o(max) c rss f 3) intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = (q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. supplying intv cc power through the extv cc switch input from an output-derived source will scale the v in current required for the driver and control circuits by the ratio (duty factor)/(efficiency). for example, in a 20v to 5v application, 10ma of intv cc current results in approxi- mately 3ma of v in current. this reduces the mid-current loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 4) the v in current has two components: the first is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control cur- rents; the second is the current drawn from the differential amplifier output. v in current typically results in a small (<0.1%) loss. other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these system level losses in the design of a system. the internal battery and input fuse resistance losses can be minimized by making sure that c in has adequate charge storage and a very low esr at the switching frequency. a 50w supply will typically require a minimum of 200 m f to 300 m f of capacitance having a maximum of 10m w to 20m w of esr. the ltc1709 2-phase architecture typically halves this input capacitance requirement over competing solutions. other losses including schottky conduction losses during dead- time and inductor core losses generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to d i load (esr), where esr is the effective series resistance of c out ( d i load ) also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc coupled and ac filtered closed loop response test point. the dc step, rise time, and settling at this test point truly reflects the closed loop response. assuming a predominantly second order system, phase margin and/or damping factor can be applicatio s i for atio wu u u 22 ltc1709-8/ltc1709-9 estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the figure 1 circuit will provide an adequate starting point for most applications. the i th series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.2 to 5 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be decided upon because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of <2 m s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the ith pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. automotive considerations: plugging into the cigarette lighter as battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during opera- tion. but before you connect, be advised: you are plugging into the supply from hell. the main battery line in an automobile is the source of a number of nasty potential transients, including load-dump, reverse-battery, and double-battery. load-dump is the result of a loose battery cable. when the cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60v which takes several hundred milliseconds to decay. reverse-battery is just what it says, while double-battery is a consequence of tow truck operators finding that a 24v jump start cranks cold engines faster than 12v. the network shown in figure 9 is the most straightfor- ward approach to protect a dc/dc converter from the ravages of an automotive power line. the series diode prevents current from flowing during reverse-battery, while the transient suppressor clamps the input voltage during load-dump. note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. although the lt1709 has a maximum input voltage of 36v, most applications will be limited to 30v by the mosfet bv dss . applicatio s i for atio wu u u figure 9. automotive application protection v in 170989 f09 12v 50a i pk rating transient voltage suppressor general instrument 1.5ka24a ltc1709 23 ltc1709-8/ltc1709-9 design example as a design example, assume v in = 5v (nominal), v in = 5.5v (max), v out = 1.8v, i max = 20a, t a = 70 c and f = 300khz. the inductance value is chosen first based on a 30% ripple current assumption. the highest value of ripple current occurs at the maximum input voltage. tie the pllfltr pin to the intv cc pin for 300khz operation. the minimum inductance for 30% ripple current is: l v fi v v v khz a v v h out out in 3 d () - ? ? ? ? 3 ()() ? ? ? ? - ? ? ? ? 3m 1 18 300 30 20 2 1 18 55 135 . % . . . a 1.5 m h inductor will produce 27% ripple current. the peak inductor current will be the maximum dc value plus one half the ripple current, or 11.4a. the minimum on- time occurs at maximum v in : t v vf v v khz s on min out in () == ()( ) =m 18 5 5 300 11 . . . the r sense resistors value can be calculated by using the maximum current sense voltage specification with some accomodation for tolerances: r mv a sense =?w 50 11 4 0 004 . . the power dissipation on the topside mosfet can be easily estimated. using a siliconix si4420dy for example; r ds(on) = 0.013 w , c rss = 300pf. at maximum input voltage with t j (estimated) = 110 c at an elevated ambient temperature: p v v cc v a pf khz w main = () + () - () [] + () ? ? ? ? () () = 18 55 10 1 0 005 110 25 0013 1755 20 2 300 300 0 65 2 2 . . . ... . w the worst-case power disipated by the synchronous mosfet under normal operating conditions at elevated ambient temperature and estimated 50 c junction tem- perature rise is: p vv v a w sync = - ? ? ? ? () w () = 55 18 55 20 2 1 48 0 013 129 2 .. . .. . a short-circuit to ground will result in a folded back current of about: i mv ns v h a sc = w + () m ? ? = 25 0 004 1 2 200 5 5 15 66 . . . . the worst-case power disipated by the synchronous mosfet under short-circuit conditions at elevated ambi- ent temperature and estimated 50 c junction temperature rise is: p vv v a mw sync = - ()() w () = 55 18 55 66 148 0013 564 2 .. . ... which is less than half of the normal, full-load dissipation. incidentally, since the load no longer dissipates power in the shorted condition, total system power dissipation is decreased by over 99%. the duty factor for this application is: df v v v v o in == = 18 5 036 . . applicatio s i for atio wu u u 24 ltc1709-8/ltc1709-9 applicatio s i for atio wu u u using figure 4, the rms ripple current will be: i inrms = (20a)(0.23) = 4.6a rms an input capacitor(s) with a 4.6a rms ripple current rating is required. the output capacitor ripple current is calculated by using the inductor ripple already calculated for each inductor and multiplying by the factor obtained from figure 3 along with the calculated duty factor. the output ripple in con tinuous mode will be highest at the maximum input voltage since the duty factor is < 50%. the maximum output current ripple is: d d i v fl at d f i v khz h a vmamv cout out coutmax rms outripple rms rms = () = () m () = =w () = 03 33 18 300 1 5 03 12 20 1 2 24 .% . . . . . pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc1709. these items are also illustrated graphically in the layout diagram of figure 10. check the following in your layout: 1) are the signal and power grounds segregated? the ltc1709 signal ground pin should return to the (C) plate of c out separately. the power ground returns to the sources of the bottom n-channel mosfets, anodes of the schottky diodes, and (C) plates of c in , which should have as short lead lengths as possible. 2) does the ltc1709 v os + pin connect to the point of load? does the ltc1709 v os C pin connect to the load return? 3) are the sense C and sense + leads routed together with minimum pc trace spacing? the filter capacitors between sense + and sense C pin pairs should be as close as possible to the ltc1709. ensure accurate current sensing with kelvin connections at the current sense resistor. 4) does the (+) plate of c in connect to the drains of the topside mosfets as closely as possible? this capacitor provides the ac current to the mosfets. keep the input current path formed by the input capacitor, top and bottom mosfets, and the schottky diode on the same side of the pc board in a tight loop to minimize conducted and radiated emi. 5) is the intv cc 1 m f ceramic decoupling capacitor con- nected closely between intv cc and the power ground pin? this capacitor carries the mosfet driver peak currents. a small value is recommended to allow placement immedi- ately adjacent to the ic. 6) keep the switching nodes, sw1 (sw2), away from sensitive small-signal nodes. ideally the switch nodes should be placed at the furthest point from the ltc1709. 7) use a low impedance source such as a logic gate to drive the pllin pin and keep the lead as short as possible. the diagram in figure 10 illustrates all branch currents in a 2-phase switching regulator. it becomes very clear after studying the current waveforms why it is critical to keep the high-switching-current paths to a small physical size. high electric and magnetic fields will radiate from these loops just as radio stations transmit signals. the output capacitor ground should return to the negative terminal of the input capacitor and not share a common ground path with any switched current paths. the left half of the circuit gives rise to the noise generated by a switching regula- tor. the ground terminations of the sychronous mosfets and schottky diodes should return to the negative plate(s) of the input capacitor(s) with a short isolated pc trace since very high switched currents are present. a separate isolated path from the negative plate(s) of the input capacitor(s) should be used to tie in the ic power ground pin (pgnd) and the signal ground pin (sgnd). this technique keeps inherent signals generated by high cur- rent pulses from taking alternate current paths that have finite impedances during the total period of the switching regulator. external opti-loop compensation allows over- compensation for pc layouts which are not optimized but this is not the recommended design procedure. 25 ltc1709-8/ltc1709-9 applicatio s i for atio wu u u figure 10. instantaneous current path flow in a multiple phase switching regulator r l v out c out + d1 l1 sw1 r sense1 v in c in r in + d2 bold lines indicate high, switching current lines. keep lines to a minimum length. l2 sw2 170989 f10 r sense2 figure 11. single and 2-phase current waveforms i cin sw v i cout i cin sw1 v dual phase single phase sw2 v i cout ripple 1709 f11 i l1 i l2 simplified visual explanation of how a 2-phase controller reduces both input and output rms ripple current a multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. the rms input ripple current is divided by, and the effective ripple frequency is multiplied up by the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). the output ripple amplitude is also reduced by, and the effective ripple frequency is increased by the number of phases used. figure 11 graphically illustrates the principle. 26 ltc1709-8/ltc1709-9 applicatio s i for atio wu u u the worst-case rms ripple current for a single stage design peaks at an input voltage of twice the output voltage. the worst-case rms ripple current for a two stage design results in peak outputs of 1/4 and 3/4 of input voltage. when the rms current is calculated, higher effective duty factor results and the peak current levels are divided as long as the currents in each stage are balanced. refer to application note 19 for a detailed description of how to calculate rms current for the single stage switch- ing regulator. figures 3 and 4 help to illustrate how the input and output currents are reduced by using an addi- tional phase. the input current peaks drop in half and the frequency is doubled for this 2-phase converter. the input capacity requirement is thus reduced theoretically by a factor of four! ceramic input capacitors with their unbeatably low esr characteristics can be used. figure 4 illustrates the rms input current drawn from the input capacitance vs the duty cycle as determined by the ratio of input and output voltage. the peak input rms current level of the single phase system is reduced by 50% in a 2-phase solution due to the current splitting between the two stages. an interesting result of the 2-phase solution is that the v in which produces worst-case ripple current for the input capacitor, v out = v in /2, in the single phase design pro- duces zero input current ripple in the 2-phase design. the output ripple current is reduced significantly when compared to the single phase solution using the same inductance value because the v out /l discharge current term from the stage that has its bottom mosfet on subtracts current from the (v in - v out )/l charging current resulting from the stage which has its top mosfet on. the output ripple current is: d i v fl dd d ripple out = -- () -+ ? ? 2 12 1 12 1 where d is duty factor. the input and output ripple frequency is increased by the number of stages used, reducing the output capacity requirements. when v in is approximately equal to 2(v out ) as illustrated in figures 3 and 4, very low input and output ripple currents result. 27 ltc1709-8/ltc1709-9 package descriptio u dimensions in inches (millimeters) unless otherwise noted. g36 ssop 1098 0.13 ?0.22 (0.005 ?0.009) 0 ?8 0.55 ?0.95 (0.022 ?0.037) 5.20 ?5.38** (0.205 ?0.212) 7.65 ?7.90 (0.301 ?0.311) 1234 5 6 7 8 9 10 11 12 14 15 16 17 18 13 12.67 ?12.93* (0.499 ?0.509) 25 26 22 21 20 19 23 24 27 28 29 30 31 32 33 34 35 36 1.73 ?1.99 (0.068 ?0.078) 0.05 ?0.21 (0.002 ?0.008) 0.65 (0.0256) bsc 0.25 ?0.38 (0.010 ?0.015) note: dimensions are in millimeters dimensions do not include mold flash. mold flash shall not exceed 0.152mm (0.006") per side dimensions do not include interlead flash. interlead flash shall not exceed 0.254mm (0.010") per side * ** g package 36-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 28 ltc1709-8/ltc1709-9 part number description comments ltc1438/ltc1439 dual high efficiency low noise synchronous step-down switching regulators por, auxiliary regulator ltc1538-aux dual high efficiency low noise synchronous step-down switching regulator auxiliary regulator, 5v standby ltc1436a-pll high efficiency low noise synchronous step-down switching regulator adaptive power tm mode, 24-pin ssop ltc1628/ltc1628-pg dual high efficiency, 2-phase synchronous step-down switching regulators constant frequency, standby, 5v and 3 .3v ldos ltc1629/ltc1629-pg polyphase high efficiency controllers expandable up to 12 phases, g-28, up to 120a ltc1929/ltc1929-pg 2-phase high efficiency controllers adjustable output up to 40a, g-28 ltc1702/ltc1703 dual high efficiency, 2-phase synchronous step-down switching regulators 500khz, 25mhz gbw ltc1708-pg dual high efficiency, 2-phase synchronous step-down switching regulator 1.3v v out 3.5v, current mode ensures with 5-bit vid and power good indication accurate current sharing, 3.5v v in 36v ltc1709 high efficiency, 2-phase synchronous step-down switching regulator 1.3v v out 3.5v, current mode ensures with 5-bit vid and fault coupling control accurate current sharing, 3.5v v in 36v ltc1709-7 high efficiency, 2-phase synchronous step-down switching regulator 0.9v v out 2v, current mode ensures with 5-bit mobile vid, and three low-current modes accurate current sharing, 3.5v v in 36v ltc1735 high efficiency synchronous step-down controller burst mode tm operation, 16-pin narrow ssop, fault protection, 3.5v v in 36v ltc1736 high efficiency synchronous step-down controller with 5-bit vid output fault protection, power good, gn-24, 3.5v v in 36v, 0.925v v out 2v adaptive power and burst mode are trademarks of linear technology corporation. linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com ? linear technology corporation 2000 170989f lt/lcg 0900 4k ? printed in usa typical applicatio u related parts figure 12. 1.3v to 3.5v/20a cpu power supply with active voltage positioning 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 runn/ss sense1 + sense1 eain pllfltr pllin nc i th sgnd v diffout v os v os + sense2 sense2 + attenout attenin vid0 vid1 nc tg1 sw1 boost1 v in bg1 extv cc intv cc pgnd bg2 boost2 sw2 tg2 pgood v bias vid4 vid3 vid2 1000pf 0.22 f ltc1709-8 m1 m2 d1 mbrs140t3 d2 mbrs140t3 v in 5v to 28v v out 1.3v to 3.5v 20a switching frequency = 200khz c in : 5a ripple current rating required c out : 4 180 f/4v panasonic sp l1 to l2: 1.5 h sumida cep125-1r5mc m1 to m4: fairchild fds7760a or siliconix si4430 10 f 0.1 f 5v (opt) 470pf vid inputs 1000pf 100pf 680pf intv cc 0.1 f 6.8k 15k 10k 2.7k 51k 0.22 f 0.1 f pgood 10 100k 10 c in 47 f 35v 0.004 0.004 m3 l2 m4 170989 f12 c out + + l1 |
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